There are three major classes of semiconductor memory: static random access memory (SRAM), dynamic random access memory (DRAM) and nonvolatile memory (NVM). Each SRAM cell contains either six transistors or four transistors and two resistors. Consequently, the area of each SRAM cell is large and the cost is high. A DRAM cell requires one transistor and one capacitor, with the capacitor consuming significant cell area and increasing manufacturing cost. Because of its smaller cell area and lower cost, DRAM enjoys a much larger market than SRAM. However, the DRAM cell, like the SRAM cell, has limited data retention.
The data, or electric charge, stored in a DRAM cell usually dissipates a few milli-seconds after the external power is turned off. The electric charge stored in a DRAM cell is also dissipated when a read operation is performed A simple writeback operation, or "refresh" following a read operation extends the validity of the data as long as external power is on.
Junction leakage in a DRAM cell also depletes the charge stored in the cell. Consequently, the refresh operation must be performed periodically, typically every several milliseconds. Because of the short refresh period and the fact that all DRAM cells need to be powered up during a refresh operation, the power needed to keep DRAM refreshed is therefore fairly high. A back-up battery to prevent data loss upon removal of the external power supply must therefore have a high capacity.
Nonvolatile SRAM has been produced with in-package battery back-up to keep the content of the memory valid when external power is removed. This battery must maintain a supply voltage V.sub.cc of one to three volts, provide power to the entire SRAM memory array and sustain all leakage and load currents. During the battery back-up mode, there is no active circuit operation.
In contrast, NVM such as EPROM, EEPROM, flash EPROM and flash EEPROM requires only a single transistor per cell. Data is stored in the form of charge inside the transistor gate oxide, with the aid of a floating polysilicon gate or layer of silicon nitride rich in charge traps. Such silicon nitride layers are presently found in metal/silicon-nitride-oxide-silicon (MNOS) or silicon-oxide-nitride-oxide-silicon (SONOS) memories. The small size of NVM cells allows for high density memory systems. Another advantage of NVM cells is that they retain their data storage content even after power supply is removed.
Traditional NVM cell construction and operation is based on the optimization of cell data retention time, programming margin and cell endurance. Data retention time, which is typically 10 years, and programming margin, which needs to be high to ensure long data retention time, are the primary concerns. In order to achieve long data retention time, the Fowler-Nordheim tunneling dielectric in such cells must have very low leakage current under normal read or disturb conditions. That is, the electron transmission coeffiecient of the Fowler-Nordheim tunneling dielectric must be sufficiently large to prevent the transfer of charge during these conditions. The tunneling dielectric therefore needs to be relatively thick. Traditional Fowler-Nordheim tunneling dielectrics used in NVM cells have an effective oxide thickness of 8 to 12 nanometers (nm) and are made of oxide, nitride or oxynitride or oxide/nitride combinations. This thick dielectric provides a significant number of charge traps. Consequently, some programming electrons in transit through the dielectric and holes generated by the high electric field (necessary to perform write/erase operations) are trapped in the dielectric material. As more write/erase operations are performed, progressively more electron trapping occurs, thereby suppressing the tunneling rate of programming electrons and causing the programming margin to deteriorate and the endurance cycle to be limited. Also, progressively more holes are trapped, thereby causing a leakage current which degrades the retention time. Eventually, the charge accumulation causes the dielectric to break down.
One drawback of NVM, compared to SRAM and DRAM, relates to write and erase speed. The write and erase speeds of NVM are about 10 microseconds and 10 milliseconds, respectively. SRAM and DRAM perform write and erase operations in approximately 20-100 nanoseconds. Thus SRAM and DRAM are much faster than traditional NVM.
Another drawback of NVM is reliability. Reliability is measured by the endurance and retention capabilities of the cell. Endurance refers to the failure of the device after repeated write and erase operations, usually due to failure of a dielectric layer through which electrons or holes pass to accomplish these operations. For this reason, EPROMs, EEPROMs, and flash EEPROMs have a limited ability to perform write and erase operations. A typical EPROM, EEPROM or flash EEPROM will suffer endurance based failure after 1,000-100,000 write/erase cycles. The other reliability issue, retention, refers to the gradual loss of data due to charge leakage over a long period of time The usual specification for NVM data retention time years. Thus, NVM has a much higher data retention time than SRAM or DRAM. It is noted that the refresh operation used for DRAM cells, where the charge stored in the cell is discharged, amplified and replenished back directly, cannot be used for NVM cells. This is because the charge stored in the NVM cell does not readily discharge, unlike the charge on the capacitor of a DRAM cell.
To overcome these drawbacks of conventional memory devices, it has been proposed to create a memory cell by coupling an EEPROM device to a DRAM device. (See, Yamauchi et al, U.S. Pat. No. 5,140,552, and Eby et al, U.S. Pat. No. 5,146,431). These memory cells, however, are not area-efficient because both an EEPROM cell and a DRAM cell must be used for each memory cell.
It is therefore desirable to have a pseudo nonvolatile memory (PNVM) cell having a high density, increased write/erase speed, and increased endurance (the best features of both volatile and non-volatile memory). It is also desirable to have a low power refresher circuit which periodically refreshes the data in the PNVM cell so that the PNVM cell may be operated in nonvolatile memory applications.